The present invention relates to a semiconductor integrated circuit device having a memory.
The memory cells of, for example, a typical DRAM (Dynamic Random Access Memory) are each comprised of a series circuit of a memory cell selection MISFET and an information storage capacitor.
High integration has been achieved in the technical field of the DRAMs so that the memory cells are yearly miniaturized more and more. These highly integrated memory cells must have their minute planes formed with the memory cell selection MISFETs and the information storage capacitors. In this case, too, the capacitors must have a capacitance no lower than a predetermined value. In order to satisfy these requirements, there have been proposed a variety of memory cells.
For example, a first DRAM is exemplified, as disclosed on pp. 592-595 of IEDM '88, by a memory cell (which will be shortly referred to as the "STC (Stacked Capacitor Cell)") which is constructed such that a first electrode of an information storage capacitor connected with a memory cell selection MISFET and a second electrode of the capacitor adapted to have a predetermined constant potential applied thereto are formed over a semiconductor substrate, and such that the first and second electrodes are laid over a gate electrode of the memory cell selection MISFET.
Next, a second DRAM is exemplified, as disclosed in U.S. Pat. No. 4,786,954 issued on Nov. 22, 1988 and assigned to Nippon Telegraph & Telephone Public Corporation, by a memory cell which is constructed such that a semiconductor substrate is formed in its principal surface with trenches, such that a first electrode of an information storage capacitor connected with a memory cell selection MISFET and a second electrode of the capacitor adapted to have a predetermined constant potential applied thereto are buried in those trenches and such that the first electrode of the capacitor and the source or drain region of the memory cell selection MISFET are connected at the side faces of the trenches.
Next, a third DRAM is exemplified, as disclosed on pp. 1257-1263 of IEEE Transactions On Electron Devices, Vol. 35, No. 8, August 1988, by a memory cell which is constructed such that a semiconductor substrate is formed in its principal surface with trenches, such that a first electrode of an information storage capacitor connected with a memory cell selection MISFET and a second electrode of the capacitor adapted to have a predetermined constant potential applied thereto are buried in those trenches, and such that the trenches have their bottoms formed with semiconductor regions for applying a predetermined constant potential to the second electrode.
Next, a fourth DRAM is exemplified, as disclosed in JP-B-58-56266 (published on Dec. 14, 1983), by a memory cell which is constructed such that a semiconductor substrate is formed in its principal surface with trenches, such that a first electrode of an information storage capacitor connected with a memory cell selection MISFET and a second electrode of the capacitor adapted to have a predetermined constant potential applied thereto are buried in those trenches, and such that a third electrode connected with the memory cell selection MISFET and made of a semiconductor region is formed on the surface portions of the trenches of the semiconductor substrate. This memory cell has its capacitance increased by a first capacitance between the first and second electrodes, a second capacitance between the second and third electrodes, and a third capacitance between the third electrode and the semiconductor substrate.
On the other hand, a structure forming an information storage capacitor by using trenches is disclosed in JP-A-51-130178 (laid-open on Nov. 12, 1976) and JP-A-59-191373 (laid-open on Oct. 30, 1984).